1. Field of the Invention
This invention relates generally to semiconductor devices, and more particularly to a semiconductor device applicable to power metal oxide semiconductor (MOS) transistor modules for use in protective circuitry of rechargeable batteries.
2. Description of Related Art
Rechargeable or secondary batteries such as lithium-ion batteries or the like are typically equipped with a protection circuit for protecting such secondary batteries against risks of overcharge/over-discharge and/or over-currents or else. A configuration of this protection circuit is schematically shown in FIG. 9. The illustrative protector circuit 100 is generally made up of a serial connection of two transistors QA and QB as connected to a secondary battery unit 200, and a control integrated circuit (IC) 300. The control IC 300 monitors a both-end voltage of the secondary battery 200 and electrical currents flowing in transistors QA and QB. Upon detection of either overcharge/overdischarge or flow of an overcurrent, IC 300 outputs a control signal (gate signal) for causing transistor QA or QB to switch from its conductive state to nonconductive state, thereby forcing secondary battery 200 to be electrically shut off from the load or from the power supply.
As demands grow for miniaturization or down-sizing of handheld wireless telephone handsets (mobile phones) or the like, such down-size demands are becoming more significant also for secondary battery protection circuitry. In the light of this trend, an attempt is made to shrink a protector circuit by arranging two MOS transistors (QA, QB) in a protector circuit as a power MOS transistor module that is packed or modularized in a single envelop or housing.
Another requirement for the transistors QA and QB making up such the protector circuit 100 is that these are low in turn-on (ON) resistivity to thereby enable mobile phones or the like with the secondary battery 200 connected thereto to run longer on a single charge-up. In the power MOS transistor module with the built-in transistors QA–QB also, it is required to have low ON resistance as an entirety of the module.
One known power MOS transistor module—i.e., first conventional art—is shown in FIGS. 10 to 12. FIG. 10 is a plan view of a power MOS transistor module in accordance with the first conventional art, and FIGS. 11–12 are cross-sectional diagrams of it as taken along lines A–A′ and B–B′ of FIG. 10, respectively.
As shown in FIG. 10, this power MOS transistor module in accordance with the first conventional art is arranged so that two transistors QA and QB each having a source region (first main electrode region) and a drain region (second main electrode region) are formed on a single piece of metal substrate (drain frame), wherein the drain regions of respective transistors QA and QB are common-coupled together by this metal substrate 50. Transistor QA includes a gate electrode 56A and source electrode 57A; transistor QB has a gate electrode 56B and source electrode 57B. The gate electrodes 56A and 56B are applied control signals (gate signals) from the above-stated controller IC 300 via gate electrode wiring lines 53. Source electrodes 57A and 57B are connected by source electrode wiring lines 54 to external elements or components (such as secondary battery 200, load or the like).
The transistors QA and QB are the so-called trench gate type MOS transistors such as shown in FIGS. 11–12. A trench-gate MOS transistor is the one that is arranged so that the sidewall of a trench gate is used as a channel region, causing a drain current to vertically flow from the source region toward the drain region being formed on the substrate's back surface. This trench-gate transistor is fabricated in a way which follows. Firstly a lightly-doped N (N−) type epitaxial layer 11 is formed on a semiconductor substrate 10 that was formed as a heavily-doped N (N+) type layer. Then, a P-type base layer 12 is selectively formed at a top surface portion of this N−-type epitaxial layer 11. Next, a gate trench 13 is formed from the surface of this P-type base layer 12 to a depth reaching the N−-type epitaxial layer 11.
Then, a gate dielectric film 14 is formed on the inner wall of this gate trench 13. Further, within this gate trench 13, a gate electrode 15 is formed by bury/embed techniques, which is made of impurity-doped polycrystalline silicon or “polysilicon.” Thereafter, an interlayer dielectric film 16 made of silicon oxide is formed at the upper part of this gate electrode 15.
Additionally, in surface portions of P-type base layer 12 each of which is interposed between gate trenches 13, N+-type source diffusion layers. 17 are selectively formed so that one layer 17 is in contact with the side face of gate trench 13. Further at a portion between such N+-type source diffusion layers 17, a P+-type diffusion layer 18 is selectively formed. In this device structure, when a gate voltage being applied to gate trench 13 is controlled, a channel is formed along this N+-type source diffusion layer 17.
This N+-type source diffusion layer 17 receives a voltage applied from the secondary battery 200 via the source electrode 57A or 57B that is formed at the upper part thereof. Trench gate 13 is given a gate signal from the controller IC 300 via gate electrode 56A or 56B in the way stated previously. Gate electrodes 56A and 56B are connected to trench gates 13 via gate polysilicon wiring lines 58 and extension leads BL (see FIG. 11 or FIG. 12 or else). Gate polysilicon wires 58 are formed above N−-type epitaxial layer 11 with a silicon oxide film 59 sandwiched therebetween. Note that gate electrode 56A (56B) and source electrode 57A (57B) are electrically isolated from each other by an interlayer dielectric film 60 and passivation film 61.
This power MOS transistor module shown in FIGS. 10–12 suffers from a limit in module shrinkage due to the presence of the thickness of metal substrate 50.
A power MOS transistor (second conventional art) with module shrinking capability is disclosed in U.S. Pat. No. 6,653,740. As shown in FIGS. 13–15, this transistor is structured so that the use of metal substrate 50 is eliminated, permitting two transistors QA and QB to share a single semiconductor substrate 10 for use as a drain region. An explanation will be given while adding in FIGS. 13–15 the same reference characters to the same parts or components as those of the first conventional art. FIG. 13 is a plan view of a power MOS transistor module in accordance with this second conventional art. FIGS. 14–15 are sectional diagrams of it as taken along lines C–C′ and D–D′ of FIG. 13, respectively.
The transistors QA and QB are similar in structure to those of the first conventional art as shown in FIG. 14; however, as shown in FIG. 15, the transistors QA and QB commonly have or “share” n+-type semiconductor substrate 10 and n−-type epitaxial layer 11. In this structure of the second conventional art, a drain current flowing between transistors QA and QB is expected to flow in this semiconductor substrate 10. Thus the metal substrate 50 such as used in the first conventional art becomes unnecessary. This makes it possible to cause the power MOS transistor module to become less in size than that of the first conventional art. Optionally in this second conventional art, an N+-type layer 62 may be provided at the boundary between transistors QA and QB overlying the N—type epitaxial layer 11.
The second conventional art circuitry is capable of meeting the need for miniaturization of power MOS transistor module as far as its ability to omit the metal substrate 50 is concerned. Unfortunately, the current flowing between two transistors QA–QB must pass through the semiconductor substrate 10, resulting in its electrical resistivity being greater than that of metal substrate 50 (FIGS. 10–12). Due to this, the ON resistance of an entirety of the power MOS transistor module becomes undesirably higher than that of the first conventional art, which leads to the lack of an ability to fully meet the requirements for reduction of power consumption.